Espressif Systems /ESP32-S3 /SPI1 /INT_RAW

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Interpret as INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PER_END_INT_RAW)PER_END_INT_RAW 0 (PES_END_INT_RAW)PES_END_INT_RAW 0 (TOTAL_TRANS_END_INT_RAW)TOTAL_TRANS_END_INT_RAW 0 (BROWN_OUT_INT_RAW)BROWN_OUT_INT_RAW

Description

SPI1 interrupt raw register

Fields

PER_END_INT_RAW

The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.

PES_END_INT_RAW

The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.

TOTAL_TRANS_END_INT_RAW

The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.

BROWN_OUT_INT_RAW

The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.

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